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Cadence reduces Renensas’ Design and verification time by 70 percent

Published: 15 January 2014 - Michelle Winny

Renesas Electronics Corporation is claimed to have shortened its design and verification time by 70 percent according to Cadence Design Systems, Inc. The company is said to have used the C-to-Silicon Compiler from Cadence to develop High Efficiency Video Coding (HEVC) intellectual property (IP), targeting consumer 4K video devices. This has enabled the company to offer IP supporting this next-generation video codec.

Renesas is thought to have established its own coding style and reduced code size by almost half with the SystemC to create the HEVC IP at a high level of abstraction. This is claimed to have enabled verification times that were six times faster than register-transfer level (RTL). This approach has also enabled Renesas to use the design platform to explore many algorithmic implementations to generate high-performance RTL while minimising power consumption and chip area.

To eliminate any potential schedule impact from a significant engineering change order (ECO) late in the project, Renesas is said to have developed an ECO flow utilising C-to-Silicon Compiler with Encounter Conformal ECO Designer. This allowed the company to use high-level synthesis to quickly apply and verify a patch to stay on schedule.

The challenge with developing this HEVC/H.265-compliant IP was to incorporate our proprietary new algorithm, which enables high quality and high compression efficiently," said Toyokazu Hori, Department Manager of Platform Base Technology Development Department, Automotive Information System Business Division at Renesas Electronics Corporation. "Deploying the system-level design approach with C-to-Silicon Compiler for the entire design addressed this challenge and we were able to implement the new algorithm very efficiently, achieving a good time-to-market for our advanced new IP."

Cadence Design Systems, Inc.

www.cadence.com

Source: Electronics


 
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