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Microchip integrates itself into the memory infrastructure market

Published: 5 August 2019 - Christian Lynn

The given complexities of artificial intelligence (AI) and machine learning, both prioritised as a result of Industry 4.0, demand an accelerated workload, the levels at which pose a problem for next-generation CPUs, which require an increased number of memory channels to deliver extended memory bandwidth for the computational purposes of their respective applications. As a result, Microchip has introduced itself into the memory infrastructure market, with its serial memory controller, the SMC 1000 8x25G. It's designed to enable CPUs and other compute-centric SoCs, to utilise four times the memory channels of parallel attached DDR4 DRAM, within the same package footprint. 

“Microchip is excited to introduce its first serial memory controller device to the market,” said Pete Hazen, VP of Microchip’s data centre solutions business unit: “New memory interface technologies, such as Open Memory Interface (OMI), enable a broad range of SoC applications to support the increasing memory requirements of high-performance data centre applications. Microchip’s entrance into the memory infrastructure market underscores our commitment to improving performance and efficiency in the data centre.”

For more information, specifications and a short video describing the product, click here.



 
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