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PHY IP platform has characterised silicon measurements

Published: 22 January 2015 - Marianne Evans

Semtech, a supplier of analog and mixed-signal semiconductors, has announced silicon proven results for its Snowbush IP analog macro operating a 25Gb/s and beyond. The new IP Platform provides lane breakouts in 2x25G (for 50Gb/s), 4x25G (for 100Gb/s) and 8x25G (for 200Gb/s) form factors.   

Big data centers are moving to upgrade their fundamental data rates with 25G+ SerDes to handle the explosion of Internet of Things (IoT) devices and large storage applications, and network solutions providers are moving toward 400Gb/s to support Zettabyte traffic. This Snowbush IP macro provides ASIC/SOC customers with the IO throughput and density needed to handle these new demands. The IP supports the recently ratified 802.3bj standard and is capable of handling electrical performance of the emerging 802.3bm and CAUI-4 standards.

“We are pleased with the excellent performance and the low power characteristics of our silicon results," said Kevin Walsh, director of worldwide marketing for the Snowbush IP brand.  "Semtech’s IP design teams continue to provide robust leading edge high speed PHY/SerDes IP that form the basis for developing cost-effective next generation SOC/ASIC chips. With a history of successful deliveries, the Snowbush IP brand continues its “go to” reputation.”


·       Proven silicon at 25Gb/s and above on TSMC 28nm HPM/HPC

·       Support for Ethernet IEEE 802.3bj with extended reach

·       Supports a broad range of data rates from 1.25Gb/s to 28.25Gb/s

·       Numerous equalisation schemes to address different channel applications and cross talk challenges

·       Automatic calibration of key circuits to maximise performance and yield

·       Robust performance with low power and low latency

·       Excellent jitter characteristics over PVT operating conditions

·       Optimised beach-front and area to meet IO throughput and density targets

About the results

The snowPHY-C2 Platform IP is measured across PVT (Process, Voltage and Temperature) and at all supported data rates and the detailed results are available in a Characterisation Report. The IP is tested with a variety of backplanes and connectors. The report details the performance details for Jitter, Power, and Reach. Techniques for on-chip process voltage and temperature variation detections and compensation make it possible to achieve reliable operation accounting for manufacturing variation. 

About the PHY

The snowPHY-C2 Platform features a full featured Analog Front End with transmit driver equalisation and a receive side CTLE, AGC, and DFE. Calibration of the AFE is performed via firmware control and offers customers the ability to modify the operation in a post silicon environment. A full set of test functions are supported with multiple loopback modes and PRBS generators. A “Scope-on-a-chip” Eye-monitor capability operates in a non-destructive way and provides user controlled granular adjustments for balancing speed of the eye construction with eye detail. The latency, power, area and beachfront of the IP macro are optimised to provide customers with four separate vectors of differentiation.

The snowPHY-C2 platform was developed in cooperation with Open-Silicon,  They also developed a test board for measurements and characterisation. 

Source: Electronics

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