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TSMC certifies Synopsys design tools

Published: 14 April 2015 - Marianne Evans

Synopsys has announced that TSMC has concluded 16 nanometer FinFET Plus (16FF+) v1.0 certification and reached the first milestone of 10nanometer (nm) certification based on the most current DRM and SPICE model on a comprehensive list of Synopsys’ custom and digital design tools. This certification enables mutual customers to deploy tools in Synopsys’ Galaxy Design Platform for 16nm production designs and 10nm early engagements.

The certified platform delivers technologies including routing rules, physical verification runsets, signoff accurate extraction technology files, statistical timing analysis that correlates with SPICE, and interoperable process design kits (iPDKs) for FinFET processes. TSMC and Synopsys have collaborated to enhance new tool features based on both 16nm and 10nm technology requirements in Synopsys’ IC Compiler II place and route solution with TSMC validation. This includes full flow colour enablement, support for connected poly on gate oxide and diffusion edge (CPODE) technology, layer optimisation, low Vdd timing closure and support for signal electro migration. The two companies are also working together to complete IC Compiler II certification for 16nm by the end of April and 10nm in June 2015.

“The combination of tool certification and our longstanding collaboration with Synopsys is enabling customers’ 16FF+ production ramp up and early engagements at 10 nanometer,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “With a full suite of TSMC certified digital, signoff, and custom implementation solutions from Synopsys, our mutual customers will achieve improved performance and lower power while attaining their time to market goals.”

“Our deep collaboration with TSMC on 16 nanometer and 10 nanometer FinFET processes allows our mutual customers to use silicon proven FinFET tools to achieve predictable design closure with faster turnaround time,” said Bijan Kiani, vice president of product marketing in Synopsys’ Design Group. “With the latest certification for these two FinFET processes, designers can take advantage of this game changing implementation technology for their next generation chip designs.”

Key Synopsys tools certified by TSMC include:

  • IC Compiler II and IC Compiler: IC Compiler is fully certified for 16FF+ production and the most current DRM and SPICE model of 10 nm. IC Compiler II certification for 16FF+ production and the 10 nm early design starts will be completed by end of April 2015 and June 2015, respectively.
  • IC Validator: Fully colour aware signoff physical verification for FinFET designs.
  • StarRC extraction solution: Multi patterning support, colour aware modelling and 3D FinFET modelling.
  • PrimeTime signoff solution: Signoff accurate delay calculation and timing analysis with advanced waveform propagation includes impact of ultra low voltage, increased Miller effect and resistivity, and process variations included in the standardised Liberty Variation Format (LVF) and multi scenario ECO guidance to accelerate timing closure and leakage recovery.
  • PrimeRail: Accurate static and dynamic IR drop analysis, colour aware electro migration and power/ground (P/G) EM rules support.
  • NanoTime: SPICE accurate transistor level static timing analysis of 10nm custom macros and embedded SRAMs.
  • DesignWare STAR Memory System: Comprehensive test, repair and diagnostics solution for Synopsys and third party embedded memories. Optimised memory test and repair algorithms provide high coverage of memory defects, including unique fault effects prevalent in FinFET based memories.
  • Galaxy Custom Designer schematic editor: Display mask colour on schematic, assign colour constraints and check schematics for colour conflicts.
  • Laker layout tool: Support for 10nm full colouring flow; reads colour constraints from Galaxy Custom Designer schematic and enforces during layout; design rule driven colour checking during layout and IC Validator integration to support colour aware verification and colour back annotation.
  • HSPICE, CustomSim and FineSim simulation products: Support for 10nm FinFET device modelling with self heating effect and delivery of accurate circuit simulation results for the latest FinFET based designs.
  • CustomSim also supports the latest design rules for electro migration, IR drop analysis and circuit electrical overstress (EOS) checking. 
Source: Micro Matters
Industry Connections: Synopsys (Northern Europe) Ltd


 
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