Cadence Sigrity 2017 delivers fast path to PCB power integrity signoff
Published: 30 January 2017 - Sarah Mead
Cadence Design Systems, has announced availability of the Sigrity 2017 technology portfolio, which introduces several key features specifically designed to speed up PCB power and signal integrity signoff. Among the features included in the newest version of the Cadence Sigrity portfolio are the Allegro PowerTree topology viewer and editor, which enable designers to quickly assess power delivery decisions early in the design cycle. The latest release of Sigrity also includes a PCI Express (PCIe) 4.0 compliance kit for checking signal integrity compliance with the latest PCIe specification when it is certified later this year.
The ability to accelerate PCB power and signal integrity signoff is not only critical for designing standalone circuit boards, but is also an important element for designing complete end products. Sigrity 2017 is one of Cadence’s System Design Enablement technologies helping companies to create innovative, high-quality electronic products from chips, to boards, to entire systems. More detail on the Sigrity 2017 portfolio may be found at cadence.com/go/Sigrity2017.
Determining the path for power delivery early in the design cycle is critical to PCB design teams. The PowerTree user interface uniquely allows for a power topology to be viewed for quick and accurate determination of the best path for power delivery. The technology also allows for easy editing as designs change. The information stored in the PowerTree environment is then used later in the design cycle to provide automated setup of post-route power integrity analysis for faster closure.
Also included in the Sigrity 2017 release is library management for power integrity models through the analysis model manager. Models can be saved and automatically retrieved from the analysis model manager library when design components are reused. This method also speeds development by automating processes that in the past have been repeatedly carried out manually.
The Sigrity 2017 release also helps designers incorporate the latest PCIe technology for high-speed interconnect as they work to ensure signal integrity. It includes a compliance kit for PCIe 4.0 interfaces in the Sigrity SystemSI™ Serial Link Analysis tool to automatically qualify signal quality standards instead of manually checking and measuring against standards documents.
“The Sigrity 2017 portfolio includes technology designed to increase efficiency and speed up the design process,” said Steve Durrill, Senior Product Engineering Group Director, Cadence. “Each of the features we’ve updated have been improved with the goal of helping our customers get high-performing products out the door faster. The work we’ve done to develop the PCIe 4.0 compliance kit even before the standard has been ratified is a visible and important example of this focus on customer requirements and time to market.”
“Teradyne has worked closely with Cadence to enable our PCB designers to take a more active role in power integrity design,” said Paul Carlin, Design Technology Group Manager. “The new updates to the Sigrity portfolio will help improve efficiencies to accelerate our product development time. This is an important advantage for Teradyne.”